New design of transistors

These are of course seminal to future in electronics industry.

The team has created a two-layer GaAs/AlGaAs quantum well heterostructure, in which the wave function of one layer extends into the second to modulate the tunneling current between the layers. In this design, a voltage on the first quantum well causes that layer to be depleted of carriers, which changes the subband energy level in the well. As the subband energy approaches the top of the quantum well potential, the wave function extends further and further out toward the second layer. When the wave function overlaps the second layer, the tunneling current can increase as much as two orders of magnitude, a substantial degree of gating leverage.

Although the reported design only works at cryogenic temperatures, a different choice of materials, for example, graphene, may allow operation at more technologically relevant temperatures. – David Voss

The mysterious Moire'- pattern-based electronic properties

Plenty of attention has been diverted to studying the bilayer graphene and hybrid structures consisting of patched mono-bi-layer graphene. A very fundamental problem in bi-layer graphene is how the electronic properties depend on the twisted angle. Theoretical study has been challenging. An interesting review in Nature on a recent PRL paper[http://www.nature.com/nature/journal/v474/n7352/full/474453a.html?WT.ec_id=NATURE-20110623#/references]:

In their study, Luican et al.⁴ find that, at small rotation angles, the local density of electronic states develops a dependence on position within the moiré-pattern unit cell and no longer exhibits the Dirac-like, decoupled-layer, Landau-level pattern. Layer coupling becomes strong in this sense for rotation angles less than about 2°, corresponding to moiré-pattern periods longer than about 10 nanometres. Here it is tempting to conjecture — from the spatial dependence of the density of electronic states — that bilayer wavefunctions have become localized, so that an STM measurement at one position reflects the stacking arrangement only at that position.
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The extraordinary sensitivity of the electronic properties of few-layer graphene systems to the relative orientations of their layers could prove useful in various applications, for example in ultra-sensitive strain gauges, pressure sensors or ultra-thin capacitors. Further progress requires an improved understanding of both large and small rotation-angle limits, and also improved experimental control of rotation angles.

Giant Electroresistance

There are many devices that are of fundamental interest. The most latest and famous may be the one invented by Fert et al., which displays giant magnetoresistance. In the past few years, there have appeared a flurry of work exploiting ferroelectrics as the barrier layer. I have mentioned quite a number of them in this blog. Here comes a new one. It is made up by sandwiching a BTO layer with two LSMO at different dopings. All these efforts are clearly directed to manipulate the interweaving properties of spin, charge and orbital degrees.

A giant tunneling electroresistance effect may be achieved in a ferroelectric tunnel junction by exploiting the magnetoelectric effect at the interface between the ferroelectric barrier and a magnetic La1 xSrxMnO3 electrode. Using first-principles density-functional theory we demonstrate that a few magnetic monolayers of La1 xSrxMnO3 near the interface act, in response to ferroelectric polarization
reversal, as an atomic-scale spin valve by filtering spin-dependent current. This produces more than an order of magnitude change in conductance, and thus constitutes a giant resistive switching effect. [PRL 106, 157203 (2011)]

Correction is more inadvertent than prevention: electronics

The statistics say that, the present rate of error occurrence is around 10^{-27}. This is imposed by the fault-tolerant architecture of logical circuits. These workers now prove that, physical fault tolerant prevention is more efficient than architectural correction in suppressing errors. [PRL 106, 176801 (2011)]

The error rate in complementary transistor circuits is suppressed exponentially in electron number, arising from an intrinsic physical implementation of fault-tolerant error correction. Contrariwise, explicit assembly of gates into the most efficient known fault-tolerant architecture is characterized by a subexponential suppression of error rate with electron number, and incurs significant overhead in wiring
and complexity.We conclude that it is more efficient to prevent logical errors with physical fault tolerance than to correct logical errors with fault-tolerant architecture.