Correction is more inadvertent than prevention: electronics

The statistics say that, the present rate of error occurrence is around 10^{-27}. This is imposed by the fault-tolerant architecture of logical circuits. These workers now prove that, physical fault tolerant prevention is more efficient than architectural correction in suppressing errors. [PRL 106, 176801 (2011)]

The error rate in complementary transistor circuits is suppressed exponentially in electron number, arising from an intrinsic physical implementation of fault-tolerant error correction. Contrariwise, explicit assembly of gates into the most efficient known fault-tolerant architecture is characterized by a subexponential suppression of error rate with electron number, and incurs significant overhead in wiring
and complexity.We conclude that it is more efficient to prevent logical errors with physical fault tolerance than to correct logical errors with fault-tolerant architecture.